1. Field of the Invention
The present invention relates to the field of programmable pass transistor configurations. More specifically, the present invention relates to a six transistor switch box.
2. Background Technology
Routing of signals from one circuit node to another is important within integrated circuits (IC) that offer programmability, such as field programmable gate arrays (FPGAs). Within an FPGA, elemental circuits blocks (e.g., input/output blocks, configurable logic blocks, etc.) are programmable to implement a host of desired functions. With this degree of flexibility, it becomes highly desirable to provide an interconnect structure that allows the elemental circuit blocks to be coupled together, i.e. so that a specific output terminal of one block can be programmably coupled to a specific input terminal of another block, and so forth. Since the positional placement of any specific circuit block is not always known, the interconnect structure needs to offer flexibility so that circuit blocks can be interconnected between a variety of different design areas.
In the past, circuit blocks have utilized a programmable six pass transistor switch circuit 55 (or "switch circuit") as shown in FIG. 1 in order to couple input and output lines. The programmable six pass transistor switch circuit is described in detail in U.S. Pat. No.4,713,557 by Carter issued on Dec. 15, 1987. As shown in FIG. 1, switch circuit 55 provides a configuration wherein four input lines (12, 14, 16, and 18) meet at a central junction site. The switch circuit 55 allows any two of these lines to be coupled together to form a signal channel. Also, provided a channel is to be formed between two lines, the switch circuit 55 allows a second channel to be formed between the other two lines.
The four lines are interconnected using a set of six programmable pass transistors. Each pass transistor is coupled at its gate to a memory cell that programs and holds the state of the transistor. The source and drains of the pass transistors are coupled to the four lines as shown in FIG. 1. The memory cell can be an SRAM, EPROM, EEPROM, flash memory, or be composed of a number of other well known programmable memory cells. Initially, each of the six transistors 10a, 20a, 30a, 40a, 50a, and 60a are turned off so that none of the four lines (12, 14, 16, and 18) are coupled at the junction site. To couple line 16 with line 12, memory cell 10b is programmed such that transistor 10a conducts. If transistor 10a is an NMOS device, then memory 10b is programmed with a "1" to turn on. If transistor 10a is a PMOS device, then memory 10b is programmed with a "0" to turn on.
To couple line 12 and line 18, memory cell 20b is programmed such that transistor 20a conducts. Likewise, lines 18 and 14 are coupled by turning on transistor 30a, lines 14 and 16 are coupled by turning on transistor 40a, lines 16 and 18 are coupled by turning on transistor 50a, and lines 12 and 14 are coupled by turning on transistor 60a. According to the above, by turning on transistors 10a and 30a, lines 16 and 12 can be coupled and simultaneously lines 18 and 14 can be coupled to form two signal channels. By turning on transistors 50a and 60a, lines 16 and 18 can be coupled and simultaneously lines 14 and 12 can be coupled to form two signal channels. Lastly, by turning on transistors 40a and 20a, lines 12 and 18 can be coupled and simultaneously lines 14 and 16 can be coupled to form two signal channels. The above programmable connections are implemented by loading the appropriate bit values into memory cells 10b, 20b, 30b, 40b, 50b and 60b.
Although switch circuit 55 of FIG. 1 provides a great deal of interconnect flexibility, each time a signal passes through a pass transistor, the transistor introduces a certain amount of resistance and capacitance. FIG. 3 shows the electrical characteristics of two pass transistors coupled in series. Specifically, FIG. 3 illustrates an exemplary pass transistor 10a having a resistance character (i.e. resistor R1) and a capacitance character (i.e. capacitor C1) coupled in series with pass transister 100A having a resistive character (i.e. resistor R2) and a capaciter character (i.e. capaciter C2). The resistance and capacitance characteristics of a pass transistor delay the propagation of the signal over a line and reduce the signal's strength. Therefore, a need arises for a mechanism for providing the flexibility of the programmable six pass gate switch box of FIG. 1 while reducing the unwanted resistance and capacitance electrical characteristics of a series of pass transistors. The present invention provides such advantageous functionality.